The present application claims priority to Japanese Application No. P11-52102 filed May 31, 1999, which application is incorporated herein by reference to the extent permitted by law.
The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having an effective pixel portion and an optical black (OPB) portion arranged in the same column.
Referring to FIG. 13, reference numeral 1 generally denotes an interline transfer CCD solid-state imaging device having a vertical optical black portion in the vertical direction of an effective pixel region known as a solid-state imaging device.
The CCD solid-state imaging device 1 has an imaging region 6 composed of an effective pixel region 4 and an optical black pixel portion (which will be hereinafter referred to as OPB portion) 5 for detecting a black level. The effective pixel region 4 has a plurality of photosensor portions 2 arranged in the form of matrix. Each photosensor portion 2 is formed by a photodiode for performing opto-electric conversion of incident light. The effective pixel region 4 further has a plurality of vertical transfer register portions 3 each having a CCD structure, respectively corresponding to the columns of the photosensors 2 in such a manner that each vertical transfer register portion 3 extends along one side of the corresponding column of the photosensor portions 2. The OPB portion 5 is formed around the effective pixel region 4 as shown by the hatching in FIG. 13 so as to be optically shielded. The solid-state imaging device 1 further has a horizontal transfer register portion 7 having a CCD structure and a charge detecting portion 8. Reference numeral 9 denotes a unit effective pixel in the effective pixel region 4.
The OPB portion 5 has a vertical OPB portion 5V formed in a vertically extended region of the effective pixel region 4. The vertical OPB portion 5V has a portion 10 corresponding to the photosensor portion 2. This portion 10 and a transfer portion corresponding to one bit of the vertical transfer register portion 3 constitute a unit optical black pixel 11. The effective pixel 9 and the optical black pixel 11 of the same column commonly have the same vertical transfer register portion 3.
In the CCD solid-state imaging device 1, signal charge obtained by opto-electric conversion at the photosensor portion 2 in the effective pixel region 4 and charge at the vertical OPB portion 5V are read to the vertical transfer register portion 3 at given periods, and then transferred toward the horizontal transfer register portion 7 by four-phase vertical driving clock pulses xcfx86V1, xcfx86V2, xcfx86V3, and xcfx86V4 (see FIG. 21), for example. In the horizontal transfer register portion 7, the charge at the vertical OPB portion 5V and the signal charge at the photosensor portion 2 both transferred from the vertical transfer register portion 3 are sequentially fed to the charge detecting portion 8 bit by bit by two-phase horizontal driving clock pulses xcfx86H1 and xcfx86H2. In the charge detecting portion 8, the input charge is converted into voltage, which is then output as a voltage signal.
Referring to FIG. 21, T1 denotes a reading time, and each of xcfx86V1 and xcfx86V3 is a ternary pulse having a reading pulse P1. xcfx86s denotes an electronic shuttering pulse, and T2 denotes an exposure time by electronic shuttering.
FIG. 14 is an enlarged plan view of the unit pixel 9 in the effective pixel region 4 shown in FIG. 13, and FIG. 15 is a cross section taken along the line C-Cxe2x80x2 in FIG. 14. FIG. 16 is an enlarged plan view of the unit optical black pixel 11 in the vertical OPB portion 5V shown in FIG. 13, and FIG. 17 is a cross section taken along the line E-Exe2x80x2 in FIG. 16.
This CCD solid-state imaging device 1 is so configured as to have a vertical overflow drain structure.
As shown in FIGS. 14 and 15, the effective pixel region 4 has the following structure. A silicon substrate 12 of first conduction type, e.g., n-type, is provided, and a first semiconductor well region 13 of second conduction type, i.e., p-type, is formed on the silicon substrate 12. An n-type semiconductor region 14 is formed on the upper surface of the first p-type semiconductor well region 13, and a p++ positive charge storage region 15 is formed on the upper surface of the n-type semiconductor region 14, so as to form the photosensor portion 2. Further, a second p-type semiconductor well region 16 and an n-type transfer channel region 17 are formed in the first p-type semiconductor well region 13 at a position separate from the photosensor portion 2. A p-type channel stop region 18 is also formed in the first p-type semiconductor well region 13.
The photosensor portion 2 as a so-called HAD (Hole Accumulation Diode) sensor is formed by the first p-type semiconductor well region 13, the n-type semiconductor region 14, and the p++ positive charge storage region 15.
The first p-type semiconductor well region 13 functions as a so-called overflow barrier region. A reading gate portion 19 is formed between the photosensor portion 2 and the vertical transfer register portion 3 to be hereinafter described. A p-type semiconductor region 20 is formed in the surface of the substrate at a position corresponding to the reading gate portion 19.
A transfer electrode 22 of polysilicon, for example, is formed through a gate insulating film 21 on the transfer channel region 17, the channel stop region 18, and the p-type semiconductor region 20 of the reading gate portion 19. The vertical transfer register portion 3 having a CCD structure is formed by the transfer channel region 17, the gate insulating film 21, and the transfer electrode 22.
Further, an interlayer dielectric 23 is formed so as to cover the transfer electrode 22, and a light shielding film 25 such as an Al film is formed on the entire surface except an opening 24 of the photosensor portion 2.
As shown in FIGS. 16 and 17, the vertical OPB portion 5V has the following structure. The n-type semiconductor region 14 mentioned above is not formed at the portion 10 corresponding to the photosensor portion 2, but only the p++ positive charge storage region 15 is formed on the upper surface of the first p-type semiconductor well region 13. Thus, no photodiode is formed at the portion 10. Further, the light shielding film 25 is formed on the entire surface including the portion 10. The other configuration is similar to that of the effective pixel region 4, so the corresponding parts are denoted by the same reference numerals and the description thereof will be omitted herein to avoid repetition.
The register width (=W0) of the vertical transfer register portion 3 in the effective pixel region 4 is set equal to the register width (=W0) of the vertical transfer register portion 3 in the vertical OPB portion 5V. The gate length (=d0) of the reading gate portion 19 in the effective pixel region 4 is set equal to the gate length (=d0) of the reading gate portion 19 in the vertical OPB portion 5V. Further, the area (=a0xc3x97b0) of the photosensor portion 2 in the effective pixel region 4 is set equal to the area (=a0xc3x97b0) of the portion 10 in the vertical OPB portion 5V.
In the CCD solid-state imaging device 1 mentioned above, the area of the photosensor portion 2 tends to be increased to improve the sensitivity with a reduction in size and an increase in number of pixels. As a result, the area of the vertical transfer register portion 3 is necessarily reduced, and the general dynamic range (corresponding to a so-called maximum handling charge amount) in the CCD solid-state imaging device 1 is determined by the dynamic range in the vertical transfer register portion 3.
As mentioned above, the portion 10 in the vertical OPB portion 5V corresponding to the photosensor portion 2 in the effective pixel region 4 has such a structure that the n-type semiconductor region 14 for forming a photodiode is not formed so as to prevent opto-electric conversion of transmitted light through the light shielding film 25, and that only the p++ positive charge storage region 15 as a p-type semiconductor region having a high impurity concentration. Accordingly, the vertical transfer register portion 3 in the vertical OPB portion 5V is strongly influenced by three-dimensional compression (clamping) from the dense p-type semiconductor region, so that the dynamic range of the vertical transfer register portion 3 in the vertical OPB portion 5V becomes smaller than the dynamic range of the vertical transfer register portion 3 in the effective pixel region 4.
This problem will now be described in more detail.
As shown in FIG. 17, the n-type semiconductor region 14 (see FIG. 15) is not formed at the portion 10 in the vertical OPB portion 5V corresponding to the photosensor portion 2 in the effective pixel region 4. Accordingly, the impurity concentration in the p++ positive charge storage region 15 formed by ion implantation is high, and the p-type impurity in the region 15 is diffused into the n-type transfer channel region 17. As a result, the effective channel width of the n-type transfer channel region 17 tends to be smaller than the channel width of the n-type transfer channel region 17 in the effective pixel region 4. On the other hand, the n-type semiconductor region 14 is present at the photosensor portion 2 in the effective pixel region 4, so that the impurity in the p++ positive charge storage region 15 is recombined in a certain amount with the impurity in the n-type semiconductor region 14. As a result, the impurity concentration in the p++ positive charge storage region 15 decreases by the certain amount, and has no influence upon the n-type transfer channel region 17.
FIG. 18 is a diagram showing a potential along the depth of the vertical transfer register portion 3 (along the line D-Dxe2x80x2 in FIG. 15) in the effective pixel region 4 at the time of normal operation. In this case, a substrate voltage Vsub is applied to the substrate 12. FIG. 19 is a diagram showing a potential along the depth of the vertical transfer register portion 3 in the effective pixel region 4 at the time of electronic shuttering. In this case, an electronic shuttering pulse xcfx86s having a positive high amplitude as shown in FIG. 21 is superimposed on the substrate voltage Vsub and applied to the substrate 12.
FIG. 20 is a diagram showing a potential along the depth of the vertical transfer register portion 3 (along the line F-Fxe2x80x2 in FIG. 17) in the vertical OPB portion 5V at the time of electronic shuttering.
When the electronic shuttering pulse xcfx86s having a positive high amplitude plus the substrate potential Vsub is applied to the substrate 12 as shown in FIGS. 19 and 20, an apparent GND potential is shifted toward positive potentials by the influence of coupling capacities C formed between the substrate 12 and the p-type regions as shown in FIGS. 15 and 17. Furthermore, the potentials in the p-type regions capacitively coupled to the substrate 12, i.e., the potential in the first p-type semiconductor well region 13 in the effective pixel region 4 and the potentials in the first and second p-type semiconductor well regions 13 and 16 in the vertical OPB portion 5V, transitionally becomes deep, causing a reduction in charge storage capacity (so-called maximum handling charge amount) of the vertical transfer register portion 3. In particular, the charge storage capacity in the vertical OPB portion 5V is most reduced at shown in FIG. 20.
This is due to the fact that the portion 10 in the vertical OPB portion 5V corresponding to the photosensor portion 2 in the effective pixel region 4 is formed by the p++ positive charge storage region 15 having a high impurity concentration as shown in FIG. 17, and that the coupling capacity C between the substrate 12 and the region 15 is therefore larger, causing a large influence on the potential at the time of application of the electronic shuttering pulse xcfx86s. As a result, the charge storage capacity of the vertical transfer register portion 3 in the vertical OPB portion 5V is most reduced.
It is accordingly an object of the present invention to provide a solid-stage imaging device which can be improved in general dynamic range.
In accordance with an aspect of the present invention, there is provided a solid-state imaging device having an effective pixel portion, an optical black portion, and a charge transfer register portion commonly provided in the effective pixel portion and the optical black portion, wherein the register width of a portion of the charge transfer register portion in the optical black portion is set larger than the register width of a portion of the charge transfer register portion in the effective pixel portion.
With this configuration, the register width of the charge transfer register portion in the optical black portion is larger than the register width of the charge transfer register portion in the effective pixel portion. Accordingly, a charge storage capacity at the charge transfer register portion in the optical black portion can be increased, so that even when a potential at the charge transfer register portion varies at the time of electronic shuttering, a sufficient charge storage capacity can be ensured. Accordingly, the general dynamic range in the solid-state imaging device can be increased.
In accordance with another aspect of the present invention, there is provided a solid-state imaging device having an effective pixel portion, an optical black portion, and a charge transfer register portion commonly provided in the effective pixel portion and the optical black portion, wherein the area of a portion in the optical black portion corresponding to a unit sensor portion in the effective pixel portion is set smaller than the area of the unit sensor portion in the effective pixel portion.
With this configuration, the area of the portion in the optical black portion corresponding to the unit sensor portion in the effective pixel portion is reduced. As a result, the distance between this portion corresponding to the unit sensor portion and the charge transfer register portion is increased. Accordingly, it is possible to reduce the influence of a coupling capacity between this portion corresponding to the unit sensor portion and the substrate upon the charge transfer register portion especially at the time of electronic shuttering, thereby suppressing variations in potential at the charge transfer register portion. Accordingly, the general dynamic range in the solid-stage imaging device can be increased.